Field of the Invention and Related Art Statement
The present invention generally relates to a semiconductor device, and more particularly to a MIS type semiconductor device for use in amplifying and switching.
Heretofore, among various MIS type semiconductor devices, the MOS FET has been considered a low voltage and low power device. However due to recent progress in semiconductor device manufacturing techniques and circuit design, it has become possible to develop a high voltage and high power MOS FET and such MOS FET has established its position in the field of semiconductor devices.
Typical constructions of the high voltage and high power MOS FET may be roughly classified into (a) off-set gate construction; (b) V-groove or U-groove construction and (c) Diffusion Self-Alignment Construction (hereinafter abbreviated as DSA). Among these constructions, the DSA construction is particularly preferable in view of the manufacturing technique and high performance.
FIG. 1A is a plan view showing a known DSA MOS FET and FIG. 1B is a cross sectional view thereof cut along a line A-A' in FIG. 1A. It should be noted that in FIG. 1A, the source electrode is wholly omitted for the sake of clearness.
In DSA MOS FET, a channel region is formed by a double diffusion and an impurity diffusion for forming the channel region (p type semiconductor layer 4) and an impurity diffusion for forming a source region (n.sup.+ type semiconductor layer 8) are effected through the same grid-like diffusion window formed in a gate poly-silicon film 6 provided on a gate oxide film 5a. The length of the channel region is defined by the difference in depth between the p type semiconductor layer 4 and n.sup.+ type semiconductor layer 8 and thus can be made extremely small e.g. smaller than a few microns. A source electrode 9 formed by a metal film deposited on an insulating film 5d is ohmic-contacted both with the n.sup.+ type semiconductor layer 8 constituting the source region and the p type semiconductor layer 4 forming the channel region. It should be noted that the source electrode 9 is actually brought into contact with a p.sup.+ type semiconductor layer 3 which is connected to the p type semiconductor region 4. In general, the gate electrode 6 is formed in the grid-like configuration or stripe-like configuration. In FIG. 1A there is shown a gate electrode of the grid-like configuration. An n.sup.+ type semiconductor substrate 1 forms a drain region and an n type semiconductor layer 2 is epitaxially grown on the substrate 1 to form a substrate of so-called n-on-n.sup.+ construction. A drain electrode not shown is formed on a rear surface of the substrate 1. When a positive voltage is applied across the source and drain, the channel region is made conductive and a current flows vertically from the substrate 1 through the channel region 4 into the source region 8.
Now the manufacturing method of the known DSA MOS FET shown in FIGS. 1A and 1B will be explained with reference to FIGS. 2A to 2F. On an n.sup.+ type silicon semiconductor substrate 1 is epitaxially grown an n type silicon semiconductor layer 2 having a resistivity of 10 to 25 .OMEGA.cm and a thickness of 30 to 60 .mu.m. Then a p.sup.+ type silicon semiconductor layer 3 is formed in the surface of epitaxial semiconductor layer 2. Next a gate oxide film 5a having a thickness of about 1,000 .ANG. is formed on the semiconductor layer 2. This condition is illustrated in FIG. 2A.
Next a poly-silicon film 6 having a thickness of about 6,000 .ANG. is deposited on the gate oxide film 5a and is selectively etched into a given pattern. Then an ion injection is effected by using the poly-silicon pattern as a mask to form a p type silicon semiconductor layer 4. FIG. 2B shows the semiconductor device at this manufacturing stage.
Next a photoresist film 7 is selectively formed by using the photoetching technique to form openings in the gate oxide film 5a at portions where a source region is to be formed later. The semiconductor device at this manufacturing stage is shown in FIG. 2C.
Then an n.sup.+ type semiconductor layer 8 constituting the source region is formed in the p type semiconductor layer 4 by ion implantation in a self-aligned manner. Then an insulating film 5b is formed during a heating process as shown in FIG. 2D. Further, a phospho-silicate glass (PSG) film 5c is formed on the insulating film 5b by the CVD method as illustrated in FIG. 2E.
Next after effecting various heating processes, openings for leading out electrodes are formed in the PSG film 5c and insulating film 5b, and then an aluminum electrode 9 is deposited and etched. In this manner there is obtained the DSA MOS FET having a source-drain breakdown voltage V.sub.DSS of about 200 to 600 volts and the construction shown in FIG. 2F. It should be noted that the double insulating films 5b and 5c are denoted by the single insulating film 5d in FIG. 1B.
In general, in the MOS FET since no accumulation of minor carriers occurs, it is possible to obtain a high switching speed, and further since the drain current has a negative temperature coefficient, it is possible to achieve a high thermal stability. These properties are particularly suitable for the high power semiconductor device. However, as compared with the bipolar transistor, the MOS FET is a majority carrier device, and thus the necessary conditions for the high breakdown property and those for high power conflict with each other. That is to say, the substrate resistance necessary for obtaining a high breakdown voltage results in an increase of the saturation voltage, so that there is a drawback in that the so-called ON-resistance becomes higher if the chip area is the same. In order to solve such a problem, it is necessary to decrease the resistance of the power passage of the FET, particularly the drain current path thereof. In other words, it is very important to increase the efficiency of the surface area of the drain. To this end, it is absolutely necessary to find an optimum pattern design by utilizing the miniaturizing process technique. DSA MOS FET has been developed to satisfy the above requirement.
However, the pattern design of the known DSA MOS FET is not optimum. It is still required to develop a gate electrode pattern i.e. poly-silicon pattern and channel configuration in which the width of the current path, i.e. the channel width which is defined as the circumferential length of the channel region can be made as long as possible within a limited silicon chip surface area. If the channel width is lengthened, the drain current can be increased and the mutual conductance g.sub.m in a large current region can be made large. This results in a decrease of the ON-resistance. Therefore, it is most important to increase the channel width within a limited area.
In the known power MOS FET of high breakdown voltage used in, for example, a switching power source, the gate poly-silicon pattern has usually a rectangular grid-like configuration as illustrated in FIG. 1A. In such a pattern the distance L.sub.2 between corners of obliquely aligned rectangular openings of the gate poly-silicon pattern is longer than the distance L.sub.1 between opposing sides of adjacent openings by .sqroot.2, i.e. L.sub.2 =.sqroot.2L.sub.1. In order to increase the channel width within a limited area, it is desired that the distances L.sub.1 and L.sub.2 be equal to each other. That is to say, since the channel region is situated along the edges of openings of the gate poly-silicon pattern, it is desired to satisfy the condition of L.sub.1 =L.sub.2 in order to make the channel width as large as possible. In the known DSA MOS FET, since L.sub.1 &lt;L.sub.2, there are large unnecessary areas in the poly-silicon film pattern in accordance with a margin of L.sub.2 -L.sub.1. This results in the gate area and thus the drain-gate capacitance being increased unnecessarily so that the switching speed is lowered.
It has been known that the channel width can be increased by miniaturizing the pattern. If the gate poly-silicon film pattern and source region are minimized, the channel width may be increased accordingly. However, in the known gate poly-silicon pattern having a rectangular grid-like configuration, the area of the opening for the source electrode is too large in comparison with the amount of drain current. If the number of channel regions is increased by the miniaturization, it is true that the channel width may be totally increased. However, the channel width within a single cell 10 becomes smaller. It should be noted that a cell is defined as a region in which the p type semiconductor layer 4 and n.sup.+ type semiconductor layer 8 are formed by using the opening in the poly-silicon film as the diffusion mask. That is to say, when the device is operated as a MOS FET under the same condition, in the device having the smaller channel width, the number of the openings for source electrode formed in the cell 10 becomes larger.
As is well known in the art, as compared with the bipolar transistor, the MOS FET is scarcely subject to thermal runaway, and the current density per cell region is smaller. Therefore, it is unnecessary to provide more than a minimum number of openings for the source electrode. It is therefore desired to design the pattern configuration in such a manner that many more channel regions can be formed by utilizing the unnecessary portions of the gate electrode and to increase the channel width.
It would be possible to increase the channel width and decrease the ON-resistance by miniaturizing the pattern. That is to say, the channel width may be increased by minimizing the surface area of the opening through which the source n.sup.+ type semiconductor layer 8 and p.sup.+ type semiconductor layer 3 connected electrically to the channel p type semiconductor layer 4 are connected to the source electrode. However, this measure has a limitation. In other words, the cell pattern could be miniaturized only to a limited extent. In the known DSA MOS FET the p type semiconductor layer 4 constituting the channel region is electrically connected to the p.sup.+ type semiconductor layer 3 and this latter layer 3 is electrically connected to the aluminum source electrode 9 together with the n.sup.+ type semiconductor layer 8 forming the source region. If the device is operated in the MOS mode without electrically connecting the p type semiconductor layer 4 to the n.sup.+ source region 8, carriers are injected from the n type semiconductor layer 2 into the p type semiconductor layer 4 and the current flows in the p type layer 4. Then the p type semiconductor layer 4 serves as the base region of the bipolar transistor and this affects the switching operation. This results in that there is a limitation in miniaturizing the source electrode lead-out portion defined by the opening formed in the gate poly-silicon film 6. Therefore, it is important to design a pattern configuration in which the surface area of the cell 10 can be made small and the channel width can be increased as far as possible.
One of the important properties of the semiconductor device is the switching speed. In order to attain a high switching speed, it is important to decrease the capacitance between the gate and drain. In order to achieve this, there have been developed typically two methods, i.e. increasing the thickness of the gate oxide film and decreasing the area occupied by the gate poly-silicon film pattern. However, in view of the threshold-voltage Vth and mutual conductance g.sub.m which define the MOS operational characteristics, there is a limitation in increasing the thickness of the gate oxide film. Therefore, the latter method, i.e. decreasing the area occupied by the poly-silicon film pattern is much more effective. This may be simply realized by thinning or miniaturizing the gate poly-silicon film pattern. However, if the poly-silicon film pattern is miniaturized, the resistance is increased accordingly and the switching speed becomes slow to an admissible extent.
Heretofore, the gate electrode has been usually formed by poly-silicon or metals having a high melting point such as molybdenum and tungsten. Since these gate materials can resist the high temperature processes, a multilayer construction has been adopted. Also in high power DSA MOS FET, the gate electrode is formed by a poly-silicon film and the aluminum source electrode is formed thereon via the insulating film so as to form the double layer electrode construction. Moreover, in order to obtain a long channel width, the gate poly-silicon film pattern has to be thinned and elongated to a large extent. As explained above, if the channel width is increased in order to decrease the ON-resistance, the gate resistance is increased and the switching speed becomes lower. Therefore, in the known DSA MOS FET, the gate resistance is decreased by providing a plurality of aluminum stripes having a high conductivity and connected to the gate poly-silicon film at the sacrifice of the channel regions. However, since between the gate aluminum electrodes there are formed the elongated poly-silicon gates having a length of several hundreds to several thousands microns, the gate resistance is still high.
Another known method for decreasing the gate resistance will be explained with reference to FIGS. 3A and 3B. In FIGS. 3A and 3B, portions similar to those shown in FIGS. 1A and 1B are denoted by the same reference numerals used in FIGS. 1A and 1B. In this known DSA MOS FET, gate and source electrode aluminum stripe patterns are provided alternately on the gate poly-silicon film via the insulating film so as to form a comb-shaped electrode configuration.
As illustrated in FIGS. 3A and 3B, the semiconductor device comprises an n.sup.+ type semiconductor substrate 1 and a first n type semiconductor layer 2 epitaxially grown on the substrate 1. A first insulating film 5a is formed on the semiconductor layer 2 and a poly-silicon film 6 is formed on the insulating film 5a. In the poly-silicon film 6 are formed openings in a grid-shape configuration. In the first semi-conductor layer 2 is formed a second p type semiconductor layer 4 in such a manner that a part of the layer 4 overlaps with a part of the poly-silicon film 6 via the first insulating film 5a. In the second layer 4 there is further formed a third n.sup.+ type semiconductor layer 8 in such a manner that a part of the third layer 8 overlaps with the poly-silicon film 6 via the first insulating film 5a. A second insulating film 5d is formed on the poly-silicon film 6 and its openings. On the second insulating film 5d are formed source and gate aluminum stripe electrodes 9a and 9b. The source electrode 9a is ohmic-contacted to the second and third semiconductor layers 4 and 8 through openings 10a formed in the second insulating film 5d and openings formed in the poly-silicon film 6. The gate electrode 9b is connected to the poly-silicon film 6 via openings 10b formed in the second insulating film 5d.
In the known DSA MOS FET shown in FIGS. 3A and 3B, having the comb-shaped electrode construction, the source Al electrode 9a and gate Al electrode 9b have to be separated from each other by a given distance by considering any lateral deviation of the patterns due to the isotropic etching for forming through-holes in the gate poly-silicon film 6 and recess between adjacent electrodes 9a and 9b. That is to say, the separation between adjacent electrodes 9a and 9b could not be effected stably due to the photo-lithography unless the pattern width of the gate poly-silicon film is thickened and the surface area of the cell is increased. In this manner, in the known DSA MOS FET there is a limitation in the miniaturization, so that the gate-source capacitance is large and the switching speed is low. As explained above, the gate resistance may be decreased to some extent by increasing the thickness of the gate poly-silicon film 6. However, then the source and gate Al electrodes 9a and 9b are liable to be cut with steep and deep steps on edges of openings formed in the poly-silicon film 6.